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IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
_______________________________________________________________________________________   3
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= (V+ - V
EE
) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = V
EE
, T
J
= 0癈 to +125癈, unless
otherwise noted. Typical values are at T
J
= +25癈. All voltages are referenced to V
EE
, unless otherwise noted.) (Note 1)
PARAMETER
YMB  L
CONDITIONS
MIN
TYP
MAX
NIT
MAX5953A/MAX5953C
7.1
Default Power Turn-On/Off
Hysteresis Voltage
V
HYST UVLO
MAX5953B/MAX5953D
4
V
External UVLO Programming
Range
V
IN,EX
MAX5953A/MAX5953C only (Note 7)
12
67
V
UVLO External Reference
Voltage
V
REF UVLO
V
UVLO
 increasing
2.400
2.460
2.522
V
UVLO External Reference
Voltage Hysteresis
V
HYST UVLO
Ratio to V
REF, UVLO
19.2
20
20.9
%
UVLO Bias Current
I
IN,UVLO
V
UVLO
 = 2.460V
-1.5
+1.5
礎
UVLO Input Ground-Sense
Threshold
V
TH G UVLO
(Note 8)
50
440
mV
UVLO Input Ground-Sense Glitch
Rejection
7
祍
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time
t
OFF_DLY
V
IN
, V
UVLO
 falling (Note 9)
0.32
ms
Isolation Switch n-Channel
MOSFET On-Resistance
R
ON,ISO
Output current = 300mA, V
GATE
 = 5.6V,
measured between OUT and V
EE
0.6
1.5
&
Isolation Switch n-Channel
MOSFET Off-Threshold Voltage
V
GSTH
V
GATE
 - V
EE
, OUT = V+,
output current < 1礎
0.5
V
GATE Pulldown Switch
Resistance
R
G
Power-off mode, V
IN
 = +12V
38
80
&
GATE Charging Current
I
GATE
V
GATE
 = 2V
4.5
10
16.5
礎
GATE High Voltage
V
GATE
I
GATE
 = 1礎
5.59
5.76
5.93
V
V
OUT
 - V
EE
 decreasing, V
GATE
 = 5.75V
1.16
1.23
1.31
V
PGOOD Assertion V
OUT
Threshold (Note 10)
V
OUTEN
Hysteresis
70
mV
V
GATE
 - V
EE
 increasing
4.62
4.76
4.91
V
PGOOD, PGOOD Assertion
V
GATE
 Threshold
V
GSEN
Hysteresis
80
mV
PGOOD, PGOOD Output Low
Voltage
V
OL PGOOD
I
SINK
 = 2mA, V
OUT
 d (V+ - 5V) (Note 11)
0.2
V
PGOOD Leakage Current
GATE = high, V+ - V
OUT
 = 67V (Note 11)
1
礎
PGOOD Leakage Current
GATE = V
EE
, PGOOD - V
EE
 = 67V
(Note 11)
1
礎
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